The present invention relates to signal timing and conductor length within integrated circuits, and more specifically, to methods, systems, and storage devices that simultaneously compare the timing of conductive signal paths in a substrate and a printed circuit board to achieve a predetermined signal timing goal.
Customers of integrated circuit chip manufacturing houses place orders for devices that have specific characteristics to achieve the customer's goals. For example, such customers may require the devices that are ordered to have time delay relationships between groups of nets (groups of wires) as they travel through flip-chip plastic ball grid array (FCPBGA) and printed circuit board wiring. Typically, customers view the substrate exclusively and ask for time delay to be added to nets whose ball grid array (BGA) pins are closest to the chip. As termination of nets moves closer to the edge of the FCPBGA, the time delay added is progressively reduced. This added delay, when considering jointly (the substrate and the board), is not needed and causes unnecessary delay to be added in the board. The embodiments described below address such issues and provide the designer visibility to propagation values of a substrate/card system.